Semiconductor memory devices are provided with a redundancy function to replace a defective memory cell with a redundancy memory cell that is a backup memory cell. Memory cell operations are tested at the time of shipment of a semiconductor memory device. Upon finding a defective memory cell, the address of this defective memory cells is recorded in a fuse circuit or the like. An address to be accessed that is applied from an external device may match the address of the defective memory cell that is recorded in the fuse circuit. Upon such an event, an access location is switched to a redundant memory cell, thereby causing the redundant memory cell, rather than the defective memory cell, to be accessed. With this arrangement, the address of the defective memory cell is made usable. In general, a redundancy replacement operation is performed on a word-line-by-word-line basis or a column-line-by-column-line basis.
The use of a redundant memory cell is avoided if this redundant memory cell is defective. To this end, a test to check the operations of a semiconductor memory device preferably includes not only a test to check primary memory cell operations but also a test to check redundant memory cell operations. With the configuration that performs a redundancy replacement on a word-line-by-word-line basis, for example, all the primary word lines and all the redundant word lines are tested for operations. Every access is performed with respect to a primary word line if no recording has been made to the fuse circuit. In order to test redundant word line operations, a test mode that specifies a redundant line test is activated. Access to a desired redundant word line is then performed by specifying an address assigned to this redundant word line.
In tests to check operations, row address (i.e., word-line address) input patterns differ depending on the types of tests. In one operation test, it may be preferable to increment the row address successively to access word lines one by one in the order in which they are arranged. In another operation test (e.g., disturb test or the like), it may be preferable to access adjacent word lines alternately.
In the operation test in which the word lines are accessed one by one in the order of arrangement, a given redundant word line and a primary word line situated physically adjacent to this redundant word line may preferably be assigned to the same row address. With the assignment of the same row address, the operation to activate a test mode to select the redundant word line and then to exit from the test mode allows the adjacent primary word line to be selected without changing the address. In such a configuration in which a redundant word line and a primary word line physically adjacent to this redundant word line are assigned to the same row address, however, an entry into and exit from the test mode may be repeated to perform the operation test in which these adjacent word lines are accessed alternately. This gives rise to a problem in that the operation test becomes lengthy.
In order to perform an operation test in which adjacent word lines are alternately accessed at high speed, it may be preferable to assign a redundant word line and a primary word line physically adjacent to this redundant word line to two different row addresses. With such an assignment of two row addresses, these two row addresses may alternately be selected in a continuing test mode to access the adjacent word lines alternately. In such a case, however, an address assigned to the redundant word line is first applied to select the redundant word line, and, then, another address separate from the above-noted address is applied to select the adjacent primary word line for the purpose of performing an operation test in which word lines are accessed one by one in the order of arrangement. Applied addresses are not continuous in this case. This gives rise to a problem in that separate address registers may be provided, one for selecting redundant word lines and another for selecting primary word lines. Further, an applied address pattern may become complex.
The description of the above-noted problems has been given with reference to the case of word-line-specific redundancy. Similar problems also arise in the case of column-line-specific redundancy. A preferable address value to be assigned to a given redundancy element (e.g., a redundant word line) may differ for different address input patterns that are used in different operation tests.
Patent Document 1 discloses a semiconductor memory in which a pseudo fuse-cut state is created on a bit-by-bit basis. This semiconductor memory includes a plurality of redundancy unit address memories, and is provided with a redundancy address memory to store a defective address assigned to a redundant word line or a redundant bit line. Patent Document 2 discloses a semiconductor memory provided with a program circuit that selects a redundancy address based on an external signal and address signals without cutting fuses. This program circuit selects redundant memory cells by use of different combinations of address signals.
[Patent Document 1] Japanese Laid-open Patent Publication No. 11-163704
[Patent Document 2] Japanese Laid-open Patent Publication No. 06-243698